Radiation Hardened Structured ASIC Platform with Compensation of Delay for Temperature and Voltage Variations for Multiple Redundant Temporal Voting Latch Technology

The invention relates to devices and methods of maintaining the current starved delay at a constant value across variations in voltage and temperature to increase the speed of operation of the sequential logic in the radiation hardened ASIC design

Methods and Devices for Modifying Active Paths in a K-Delta-1-Sigma Modulator

The invention relates to an improved K-Delta-1-Sigma Modulators (KG1Ss) that achieve multi GHz sampling rates with 90 nm and 45 nm CMOS processes, and that provide the capability to balance performance with power in many applications. The improved KD1Ss activate all paths when high performance is needed (e.g. high bandwidth), and reduce the effective bandwidth by shutting down multiple paths when low performance is required. The improved KD1Ss can adjust the baseband filtering for lower bandwidth, and can provide large savings in power consumption while maintaining the communication link, which is a great advantage in space communications. The improved KD1Ss herein provides a receiver that adjusts to accommodate a higher rate when a packet is received at a low bandwidth, and at a initial lower rate, power is saved by turning off paths in the KD1S Analog to Digital Converter, and where when a higher rate is required, multiple paths are enabled in the KD1S to accommodate the higher band widths

High resolution frequency to time domain transformations applied to the stepped carrier MRIS measurements

Two narrow-band radar systems are developed for high resolution target range estimation in inhomogeneous media. They are reformulations of two presently existing systems such that high resolution target range estimates may be achieved despite the use of narrow bandwidth radar pulses. A double sideband suppressed carrier radar technique originally derived in 1962, and later abandoned due to its inability to accurately measure target range in the presence of an interfering reflection, is rederived to incorporate the presence of an interfering reflection. The new derivation shows that the interfering reflection causes a period perturbation in the measured phase response. A high resolution spectral estimation technique is used to extract the period of this perturbation leading to accurate target range estimates independent of the signal-to-interference ratio. A non-linear optimal signal processing algorithm is derived for a frequency-stepped continuous wave radar system. The resolution enhancement offered by optimal signal processing of the data over the conventional Fourier Transform technique is clearly demonstrated using measured radar data. A method for modeling plane wave propagation in inhomogeneous media based on transmission line theory is derived and studied. Several simulation results including measurement of non-uniform electron plasma densities that develop near the heat tiles of a space re-entry vehicle are presented which verify the validity of the model

Optimal Signal Processing of Frequency-Stepped CW Radar Data

An optimal signal processing algorithm is derived for estimating the time delay and amplitude of each scatterer reflection using a frequency-stepped CW system. The channel is assumed to be composed of abrupt changes in the reflection coefficient profile. The optimization technique is intended to maximize the target range resolution achievable from any set of frequency-stepped CW radar measurements made in such an environment. The algorithm is composed of an iterative two-step procedure. First, the amplitudes of the echoes are optimized by solving an overdetermined least squares set of equations. Then, a nonlinear objective function is scanned in an organized fashion to find its global minimum. The result is a set of echo strengths and time delay estimates. Although this paper addresses the specific problem of resolving the time delay between the first two echoes, the derivation is general in the number of echoes. Performance of the optimization approach is illustrated using measured data obtained from an HP-X510 network analyzer. It is demonstrated that the optimization approach offers a significant resolution enhancement over the standard processing approach that employs an IFFT. Degradation in the performance of the algorithm due to suboptimal model order selection and the effects of additive white Gaussion noise are addressed

On the Effect of Input Signal Correlation on Weight Misadjustment in the RLS Algorithm

New expressions are derived for the mean weight misadjustment in the recursive least squares (RLS) algorithm for first-order Markov channel estimation. The expressions derived are general in that they take into account the correlation in the input. It is shown that the additive system noise is amplified by a correlation amplification factor that is defined as a function of the input autocorrelation matrix eigenvalues. However, input correlation has almost no effect on the misadjustment due to time-varying system weights. These results are checked by simulations demonstrating excellent agreement with the theory. Keywords--- RLS algorithm, effect of input correlation, error analysis. I. Introduction This correspondence considers the steady-state analysis of the RLS algorithm for the general case in which the input to the adaptive filter can be correlated. In most of the work analyzing the performance of adaptive filters, authors have made the assumption that the input is composed of i..

Analysis of a Stabilization Technique for the Fixed-Point Prewindowed RLS Algorithm

In this correspondence, a stable finite precision Recursive Least Squares (RLS) algorithm is derived for the prewindowed growing memory case (forgetting factor, = 1). Previously, it has been shown that the prewindowed growing memory RLS algorithm diverges under fixed-point implementation [1, 2]. The random walk phenomenon due to roundoff errors in the weight update causes the divergence of the algorithm. To overcome this effect, these roundoff errors are modeled such that their effect is incorporated into the algorithm. The steady-state behavior of this new algorithm is analyzed, and it is shown that the divergence phenomenon is actually eliminated, and the new algorithm converges. I. Introduction It has been shown that, for the prewindowed RLS algorithm ( = 1), the roundoff error associated with the weight update recursion leads to divergence as the algorithm iterates, [1, 2]. In the literature, this phenomenon has been explained as a random walk process for the weight vector [2, 7..

Radiation Hardened by Design 8 bit RISC with Dual I2C Bus Support and SPI for External NVM Support

The Mini-PnP 3x3 mm ASIC has been designed with Radiation Hardened by Design (RHBD) techniques using the IBM9LP CMOS process. The chip includes a high performance 8 bit PIC based RISC with 4Kx14 EDAC protected on chip Instruction RAM and two banks of registers supporting 192 bytes each. The registers are implemented using temporal latch technology and are SEU immune. The architecture supports two master inter-integrated circuit (I2C) buses where one can be configured as an I2C slave. The chip implements a SPI Master core. The cores are integrated with the RISC processor using a Wishbone Bus Crossbar switch. Mini-PnP ASIC supports bootup from an external SPI based Non Volatile Memory (NVM). The reading of the “eXtensible Transducer Electronic Datasheet” (xTEDS) from the external SPI NVM is also supported for Plug and Play applications. The ASIC Mini- PnP Silicon has been successfully tested with the design clock of 50 MHz. In this paper, the power consumption of the core power versus clock scaling is presented. The goal of the multi-chip module (MCM) implementation of Mini-PnP is to reduce the system size to around 15x15mm with integrated ASIC Mini-PnP, I2C driver circuits, SPI NVM (128Kbytes), and multiplexing to support external programming of the SPI NVM. A Chip on Board (COB) solution will be presented